|
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Макроопределения |
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_UTIL_TWI_H_ 1 |
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TWSR values |
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Mnemonics: |
|
#define |
TW_START 0x08 |
#define |
TW_REP_START 0x10 |
#define |
TW_MT_SLA_ACK 0x18 |
#define |
TW_MT_SLA_NACK 0x20 |
#define |
TW_MT_DATA_ACK 0x28 |
#define |
TW_MT_DATA_NACK 0x30 |
#define |
TW_MT_ARB_LOST 0x38 |
#define |
TW_MR_ARB_LOST 0x38 |
#define |
TW_MR_SLA_ACK 0x40 |
#define |
TW_MR_SLA_NACK 0x48 |
#define |
TW_MR_DATA_ACK 0x50 |
#define |
TW_MR_DATA_NACK 0x58 |
#define |
TW_ST_SLA_ACK 0xA8 |
#define |
|
#define |
TW_ST_DATA_ACK 0xB8 |
#define |
TW_ST_DATA_NACK 0xC0 |
#define |
TW_ST_LAST_DATA 0xC8 |
#define |
TW_SR_SLA_ACK 0x60 |
#define |
|
#define |
TW_SR_GCALL_ACK 0x70 |
#define |
|
#define |
TW_SR_DATA_ACK 0x80 |
#define |
TW_SR_DATA_NACK 0x88 |
#define |
TW_SR_GCALL_DATA_ACK 0x90 |
#define |
|
#define |
TW_SR_STOP 0xA0 |
#define |
TW_NO_INFO 0xF8 |
#define |
TW_BUS_ERROR 0x00 |
#define |
|
#define |
TW_STATUS (TWSR
& TW_STATUS_MASK) |
R/~W
bit in SLA+R/W address field. |
|
#define |
TW_READ 1 |
#define |
TW_WRITE 0 |
Automatically generated by Doxygen 1.5.2 on 21
Dec 2007.